FPGA Development
AMD (Xilinx), Intel (Altera), and Microsemi FPGA design with automated build chains and timing closure
Key Capabilities
- Xilinx/AMD: Zynq-7000, Zynq UltraScale+, RFSoC families and others
- Intel/Altera: Cyclone V, Stratix II/III, MAX II and others
- Microsemi: SmartFusion II and others
- Automated build systems: TCL scripting, version control, CI/CD integration
- Simulation and model-driven verification methodologies
- Timing closure through architectural design, SDC constraints, and systematic optimisation
- DSP implementations: channelisers, CORDIC, filters, signal processing chains
- High-speed interfaces: PCIe, multi-gigabit SERDES, 100+ Gbps Ethernet, custom protocols
- Embedded Linux driver development and AXI fabric integration
- Hardware and software co-design and system-level integration
- Data flow architecture: backpressure handling, packetisation, buffer management
- Multi-channel synchronisation and phase alignment for beamforming applications
FPGA Development
FPGA development often suffers from problematic workflows: GUI-driven design environments that resist version control, build processes that take hours without reproducibility, and timing failures discovered late in development cycles. Many teams treat FPGAs like software projects without respecting hardware realities — combinational logic sprawl, clock domain violations, and designs that force place and route tools into impossible optimisation problems. The result: extended debug cycles where engineers cannot distinguish timing errors from functional logic errors, and a lack of verification testbenches to compare with on-chip debug cores.
Dagny Labs approaches FPGA development as hardware design executed with software engineering discipline. Projects are structured with TCL scripting for reproducible builds, version controlled RTL with test bench coverage, and makefiles that integrate into CI/CD pipelines. Designs are validated in simulation, and where required for DSP designs, against Python or MATLAB reference implementations before hardware deployment. Clock domains are properly isolated with dual-clock FIFOs. Combinational logic is minimised. Reset strategies avoid race conditions between system domains. Timing closure is achieved through architectural decisions, not seed randomisation lotteries.
Experience spans Xilinx/AMD devices (Zynq-7000, Zynq UltraScale+, RFSoC families), Intel/Altera platforms (Cyclone V, Stratix II/III), and Microsemi SmartFusion II, but other devices are welcome. Work includes designs approaching million-logic-cell utilisation with 20+ clock domains, high-speed transceiver interfaces, and 100+ Gbps Ethernet integration. DSP specialisations include polyphase channelisers, CORDIC implementations, digital filter chains, and complete signal processing pipelines.
The cross-domain capability extends beyond RTL design. Embedded Linux driver development for FPGA SoCs enables AXI fabric integration and userspace application interfaces. Understanding the complete signal chain — RF frontend through data conversion, acquisition, processing, and output — provides a system-level perspective. This is explored further in the Electronics Design, DSP Design, and Embedded Development service pages.
Industry Experience
Practical experience across defence radar systems, high-speed networking infrastructure, vision systems, and data acquisition platforms provides understanding of FPGA applications beyond academic exercises.
Twenty years of FPGA development across defence and commercial sectors — from compact Cyclone implementations to resource-maximised UltraScale+ designs — demonstrates that systematic engineering discipline produces reliable results. The ability to traverse the complete system stack from hardware interfaces through RTL implementation to embedded software integration separates competent FPGA work from narrow technical execution.
Reach Out
Need validated FPGA firmware? Please make contact to see if there is a fit.