DSP Design
Python modelling to hardware implementation with resource-optimised algorithms
Key Capabilities
- Python and MATLAB modelling with custom signal chain frameworks
- Polyphase channeliser design for multi-channel receiver systems
- CORDIC implementations for mixing, tuning, and quadrature modulation
- Cascaded filtering: CIC with compensation, FIR with decimation/interpolation
- Resource optimisation: multiplier utilisation, memory management, pipeline architecture
- Fixed-point arithmetic and bit growth management for dynamic range optimisation
- Complete signal chain understanding: RF through FPGA to embedded software control
DSP Design
Digital signal processing implementation frequently suffers from a fundamental disconnect: algorithms designed without understanding hardware constraints, FPGA implementations developed without validated mathematical models, and systems debugged without the ability to isolate whether artefacts originate in analog electronics, data conversion, or FPGA firmware. The result is wasted silicon resources processing noise, uncertain performance characteristics, and extended debug cycles chasing problems across domain boundaries.
Dagny Labs approaches DSP design through systematic progression from mathematical modelling to hardware validation. Python-based signal chain frameworks model complete RF paths — noise characteristics, converter performance, and processing algorithms — before hardware implementation begins. This methodology enables requirement-driven resource allocation: calculating multiplier utilisation, memory bandwidth, pipeline depth, and FPGA architecture before writing HDL. The approach links directly to the verification practices described in the FPGA Development service page, where simulation validates functionality before hardware deployment.
Implementation experience spans polyphase channelisers for multi-channel systems, CORDIC-based mixing and quadrature modulation, cascaded CIC and FIR filtering with compensation, and complete wideband-to-narrowband processing chains for Rx and narrowband-to-wideband processing for Tx. Designs handle GSPS sample rates from RF data converters (including RFSoC platforms and JESD204B serial interfaces) down to kHz narrowband outputs with appropriate dynamic range management. Resource optimisation involves architectural decisions — parallelisation versus time-multiplexing, vendor DSP block utilisation versus custom logic, buffer sizing for backpressure management — informed by calculated requirements rather than conservative over-design.
The cross-domain integration capability extends beyond isolated DSP work. Oscillator phase noise characteristics determine data converter performance, which dictates processing requirements and achievable dynamic range. Understanding this complete signal chain — from RF front-end design through analog-to-digital conversion to FPGA implementation to embedded software control — enables system-level optimisation.
Industry Experience
Experience with Python and MATLAB-based signal chain modelling, HDL implementation on high-end FPGA platforms, and hardware integration provides the skill set required for successful DSP deployment. The value lies not in deep specialisation within narrow algorithm families, but in sound engineering principles applied across the complete implementation chain from mathematical concept to functioning hardware.
Reach Out
Have a DSP need? Please make contact to see if there is a fit.